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Some of the material in is restricted to members of the community. By logging in, you may be able to gain additional access to certain collections or items. If you have questions about access or logging in, please use the form on the Contact Page.
Conditional branches have traditionally been a performance bottleneck for most processors. The high frequency of branches in code coupled with expensive pipeline flushes on mispredictions make branches expensive instructions worth...
Processors that employ instruction fusion can improve performance and energy usage beyond traditional processors by collapsing and simultaneously executing dependent instruction chains on the critical path. This paper describes compiler...
Energy efficiency is an important design consideration in nearly all classes of processors, but is of particular importance to mobile and embedded systems. The data cache accounts for a significant portion of processor power. We have...
Statically pipelined processors offer a new way to improve the performance beyond that of a traditional in-order pipeline while simultaneously reducing energy usage by enabling the compiler to control more fine-grained details of the...
DAGDA exposes some of the hidden operations that the hardware uses when performing loads and stores to the compiler to save energy and increase performance. We decouple the micro-operations for loads and stores into two operations: the...
Some of the material in is restricted to members of the community. By logging in, you may be able to gain additional access to certain collections or items. If you have questions about access or logging in, please use the form on the Contact Page.
