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Level-one data cache (L1 DC) accesses impact energy usage as they frequently occur and use signif icantly more energy than register ﬁle accesses. Modern processors use virtually-indexed, physically tagged caches to reduce the L1 DC access time at the expense of increasing the energy to access it. It has been estimated that 28% of embedded processor energy is due to data supply . In addi tion, level-one data caches have a signiﬁcant impact on performance as a hit in the level-one data cache avoids accessing higher levels of the memory hierarchy, which typically have longer access times. Modern processors employ strategies such as critical-word ﬁrst as well as lockup-free caches to limit the penalty of an L1 DC miss. However, as the issue-width of a processor is increased, the number of cycles that can be overlapped with a L1 DC line ﬁll is decreased. This dissertation provides techniques that reduce both the energy usage of level-one data caches as well as improves the performance of processors by reducing the number of stalls due to loads and stores.