Reducing Power Involved in Pipeline Scheduling Through the Use of an Incremental Hybrid Scheduler

When considering computer processors, there is a trade-off between performance and power; improved performance does not typically come without an increase in power. Similarly, the reduction of power often times means a reduction in performance. This paper proposes an approach that realizes both high performance and low power levels. The approach involves an incremental hybrid scheduler. The hybrid scheduler takes advantage of the already low-power Tagless-Hit Instruction Cache (TH-IC), by caching instruction schedules. This eliminates many unnecessary creations of redundant schedules. Additionally, the hybrid scheduler essentially runs in a low-power in-order mode and switches to a more aggressive scheduling mode only when in the code hot spots. The hybrid scheduler offers a simple approach to gain improvements in performance as compared to an in-order processor while still maintaining a low power level.