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Implementation of digital filters in Field Programmable Gate Arrays (FPGAs) requires many multipliers, which is directly related to the implementation cost. This research is devoted towards efficient implementation of digital filters in FPGAs using Multiple Constant Multiplication (MCM). Our work results in reducing the area required to implement digital filters reduced in terms of Configurable Logic Blocks (CLBs) usage. Multiple constant multiplication is used to realize a number of constant multiplications using minimum number of adders/ subtractors and shifts. Multiplier blocks can be designed using different MCM algorithms. This research involves studying various MCM algorithms and their effect on digital filter implementation in FPGAs. Practical implementation of the Difference Adder Graph (DIFFAG) algorithm is explored in this work. Research also includes efficient implementation of the loop filter for delta-sigma converter for noise shaping in FPGA chip. Results obtained in this work show that that DIFFAG uses fewer number of adders to design a multiplier block for our loop filter than other MCM algorithms. The Xilinx Vertex-4 FPGA is a target device for implementation of the loop filter. Vertex-4 devices provide a good platform for DSP applications. Implementation of various order high pass FIR filters are also analyzed in this work. The high pass FIR filters are designed in VHDL using the HCUB algorithm and are synthesized using Vertex-4 chip. Results achieved through this research show that FPGA implementation of digital filters using MCM results in significant area savings.