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Energy efficiency is an important design consideration in nearly all classes of processors, but is of particular importance to mobile and embedded systems. The data cache accounts for a significant portion of processor power. We have previously presented an approach to reducing cache energy by introducing an explicitly controlled tagless access buffer (TAB) at the top of the cache hierarchy. The TAB reduces energy usage by redirecting loop memory references from the level-one data cache (L1D) to the smaller, more energy-efficient TAB. These references need not access the data translation lookaside buffer (DTLB), and can sometimes avoid unnecessary transfers from lower levels of the memory hierarchy. We improve upon our previous design to create a system that requires fewer instruction set changes and gives more explicit control over the allocation and deallocation of TAB resources. We show that with a cache line size of 32 bytes, a four-line TAB can eliminate on average 31% of L1D accesses, which reduces L1D/DTLB energy usage by 19%.