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In recent years, the need to reduce the power and energy requirements of computer microprocessors has increased dramatically. In the past, microprocessor architects succeeded in improving the performance of their designs by increasing clock frequency, and building wider and deeper pipelines. These design choices inevitably lead to increased power and energy usage, and thus increased heat dissipation. With the proliferation of battery-powered embedded and mobile computer systems, it is necessary to reduce energy usage without sacrificing performance. This dissertation analyzes two architectural techniques that are designed to reduce the energy usage required to complete computational tasks, without impacting performance. The first technique is the Tagless-Hit Instruction Cache (TH-IC), which reduces energy used for fetching instructions by disabling several large fetch-related structures when it can be guaranteed they are not needed. The second is Static Pipelining, which reduces power by moving much of the pipeline control from pipeline logic to the compiler. These techniques have previously been studied with high level, architectural models based on the Sim-Wattch simulator. Such models estimate total energy usage by attributing a usage to various architectural events. The energy for each event must be derived from actual physical models of those components, and will be inaccurate if energy usage is dependent on factors that cannot be summarized by a single energy value per event. In addition, issues such as circuit timing and fabrication technology cannot be considered by the model without designing the real circuit it represents. This dissertation presents an analysis of physical models of a traditionally-architected 5-stage OpenRISC processor, an implementation of the TH-IC, and a statically pipelined processor, all of which have been created from scratch using a hardware definition language and computer aided design tools. The OpenRISC processor serves as a baseline for comparison versus the statically pipelined processor. Additionally, the RISC processor is examined both with and without the TH-IC. Accurate estimates of energy usage and timing are derived using these models.