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This thesis describes an architectural visualization tool developed to illustrate the instruction flow in a modern processor pipeline simulation. It was designed to aid in better understanding the complexities of a modern pipeline design. The visualizer allows the user to control the execution of the simulator by stepping ahead cycles in execution as well as setting breakpoints and watchpoints on microarchitected state data. The visualizer can also display the contents of microarchitected state at any time, enabling careful analysis of the state of the simulator. We believe that these features within the visualizer will allow a developer to more easily analyze the effects of a new compiler optimization or microarchitectural addition in more depth than typical simulator statistical data provides. Furthermore, we feel the visualizer is a valuable teaching aid in computer architecture classes, as it allows students to interactively visualize the control and data flow of a program through a particular pipeline design. Lastly, the visualizer was created in such a way to provide easier interfacing to other simulators.
User Interface, Debugging, Visualization Tool, Computer Architecture
Date of Defense
April 4, 2007.
Submitted Note
A Thesis submitted to the Department of Computer Science in partial fulfillment of the requirements for the degree of Master of Science.
Bibliography Note
Includes bibliographical references.
Advisory Committee
Gary Tyson, Professor Co-Directing Thesis; David Whalley, Professor Co-Directing Thesis; Xin Yuan, Committee Member.
Publisher
Florida State University
Identifier
FSU_migr_etd-3449
Use and Reproduction
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