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A Power Hardware-in-the-Loop (PHIL) simulation should be accurate to truly reflect the behavior of the systems under test. However, a PHIL simulation may result in errors or even instability due to imperfections (e.g., time delay, noise injection, phase lag, limited bandwidth) in the power interface. This issue is especially problematic in high power applications. Additionally, it is usually difficult to determine the accuracy of simulation results because there is no reference available. Consequently, a method is needed to evaluate the accuracy of PHIL simulations. In this thesis, an effective method for evaluating the accuracy of PHIL simulations is proposed. This method provides a means to justify the result of a PHIL simulation analytically and quantitatively instead of empirically. In the derivation of the method, it is also found that the magnitude of the system's open loop transfer function can be taken as one of the most important performance indices for evaluating different interface algorithms. This conclusion is significantly useful for the selection of the optimal interface algorithms and for the future design of advanced interface algorithms. Although the proposed method is derived based on linear system analysis, it is shown to be effective for many nonlinear systems also. Simulations and experiments are performed for the purpose of validation. Limitations of the method are also discussed. For cases where the proposed method fails to be effective, a simulation-only method is proposed and explained as the future work.
Simulation Accuracy, HIL Hardware-in-the-Loop Simulation, Interface Algorithm
Date of Defense
July 2, 2007.
Submitted Note
A Dissertation Submitted to the Electrical and Computer Engineering Department in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy.
Bibliography Note
Includes bibliographical references.
Publisher
Florida State University
Identifier
FSU_migr_etd-1885
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