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Improving Processor Efficiency Through Enhanced Instruction Fetch

Title: Improving Processor Efficiency Through Enhanced Instruction Fetch.
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Name(s): Hines, Stephen R. (Stephen Roderick), 1979-, author
Whalley, David, professor co-directing dissertation
Tyson, Gary, professor co-directing dissertation
Erlebacher, Gordon, outside committee member
Van Engelen, Robert, committee member
Kumar, Piyush, committee member
Wang, Andy, committee member
Department of Computer Science, degree granting department
Florida State University, degree granting institution
Type of Resource: text
Genre: Text
Issuance: monographic
Date Issued: 2008
Publisher: Florida State University
Place of Publication: Tallahassee, Florida
Physical Form: computer
online resource
Extent: 1 online resource
Language(s): English
Abstract/Description: Instruction fetch is an important pipeline stage for embedded processors, as it can consume a significant fraction of the total processor energy. This dissertation describes the design and implementation of two new fetch enhancements that seek to improve overall energy efficiency without any performance tradeoff. Instruction packing is a combination architectural/compiler technique that leverages code redundancy to reduce energy consumption, code size, and execution time. Frequently occurring instructions are placed into a small instruction register file (IRF), which requires less energy to access than an L1 instruction cache. Multiple instruction register references are placed in a single packed instruction, leading to reduced cache accesses and static code size. Hardware register windows and compiler optimizations tailored for instruction packing yield greater reductions in fetch energy consumption and static code size. The Lookahead Instruction Fetch Engine (LIFE) is a microarchitectural technique designed to exploit the regularity present in instruction fetch. The nucleus of LIFE is the Tagless Hit Instruction Cache (TH-IC), a small cache that assists the instruction fetch pipeline stage as it efficiently captures information about both sequential and non-sequential transitions between instructions. TH-IC provides a considerable savings in fetch energy without incurring the performance penalty normally associated with small filter instruction caches. Furthermore, TH-IC makes the common case (cache hit) more energy efficient by making the tag check unnecessary. LIFE extends TH-IC by making use of advanced control flow metadata to further improve utilization of fetch-associated structures such as the branch predictor, branch target buffer, and return address stack. LIFE enables significant reductions in total processor energy consumption with no impact on application execution times even for the most aggressive power-saving configuration. Both IRF and LIFE (including TH-IC) improve overall processor efficiency by actively recognizing and exploiting the common properties of instruction fetch.
Identifier: FSU_migr_etd-4036 (IID)
Submitted Note: A Dissertation submitted to the Department of Computer Science in partial fulfillment of the requirements for the degree of Doctor of Philosophy.
Degree Awarded: Summer Semester, 2008.
Date of Defense: June 27, 2008.
Keywords: Tagless Hit Instruction Cache, Instruction Packing, Instruction Register File, Compilers, Architecture, Instruction Fetch, Lookahead Instruction Fetch Engine
Bibliography Note: Includes bibliographical references.
Advisory Committee: David Whalley, Professor Co-Directing Dissertation; Gary Tyson, Professor Co-Directing Dissertation; Gordon Erlebacher, Outside Committee Member; Robert van Engelen, Committee Member; Piyush Kumar, Committee Member; Andy Wang, Committee Member.
Subject(s): Computer science
Persistent Link to This Record: http://purl.flvc.org/fsu/fd/FSU_migr_etd-4036
Owner Institution: FSU

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Hines, S. R. (S. R. ). (2008). Improving Processor Efficiency Through Enhanced Instruction Fetch. Retrieved from http://purl.flvc.org/fsu/fd/FSU_migr_etd-4036