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Efficient Hardware Implementation Techniques for Digital Filters

Title: Efficient Hardware Implementation Techniques for Digital Filters.
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Name(s): Guo, Rui, 1984-, author
DeBrunner, Linda, professor directing dissertation
Harvey, Bruce, committee member
DeBrunner, Victor, committee member
Roberts, Rodney, committee member
Department of Electrical and Computer Engineering, degree granting department
Florida State University, degree granting institution
Type of Resource: text
Genre: Text
Issuance: monographic
Date Issued: 2011
Publisher: Florida State University
Place of Publication: Tallahassee, Florida
Physical Form: computer
online resource
Extent: 1 online resource
Language(s): English
Abstract/Description: This dissertation addresses the development of efficient digital filter implementation techniques. Measures for area, latency, and throughput are used to quantify the benefits of the proposed implementation schemes, as well as consideration of the digital signal processing algorithm performance. Multiple-constant multiplication (MCM) is a popular approach for implemented fixed coefficient finite impulse response (FIR) filters. We propose two methods for truncating addition results in an MCM implementation that reduce the area required while decreasing latency. The effects of filter order and coefficient quantization are explored by the proposed search technique that reduces the computations required by an MCM implementation. Two new adaptive filter implementation techniques based on distributed arithmetic (DA) are proposed that provide reduced area and speed without loss of filter performance. Adaptive filter implementations can also be based on real-time conversion of the adapted coefficients into a canonical-signed-digit (CSD) representation. We propose a new conversion circuit that reduces both latency and area. Fine-grained parallelism and relaxed look-ahead techniques are applied to develop a pipelined Gauss-Seidel fast affine projection (GSFAP) adaptive filter implementation that allow degradation to the adaptive filter performance and increases area to achieve significantly faster performance. These proposed techniques for fixed coefficient and adaptive filters can be used for applications in which low area and high speed implementations are required.
Identifier: FSU_migr_etd-3897 (IID)
Submitted Note: A Dissertation submitted to the Department of Electrical and Computer Engineering in partial fulfillment of the requirements for the degree of Doctor of Philosophy.
Degree Awarded: Summer Semester, 2011.
Date of Defense: June 29, 2011.
Keywords: Pipelining, Distributed Arithmetic, Digital Filter
Bibliography Note: Includes bibliographical references.
Advisory Committee: Linda DeBrunner, Professor Directing Dissertation; Bruce Harvey, Committee Member; Victor DeBrunner, Committee Member; Rodney Roberts, Committee Member.
Subject(s): Electrical engineering
Computer engineering
Persistent Link to This Record: http://purl.flvc.org/fsu/fd/FSU_migr_etd-3897
Owner Institution: FSU

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Guo, R. (2011). Efficient Hardware Implementation Techniques for Digital Filters. Retrieved from http://purl.flvc.org/fsu/fd/FSU_migr_etd-3897