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Minimizing FIR Filter Designs Implemented in FPGAs Utilizing Minimized Adder Graph Techniques

Title: Minimizing FIR Filter Designs Implemented in FPGAs Utilizing Minimized Adder Graph Techniques.
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Name(s): Howard, Charles D., author
DeBrunner, Linda S., professor directing thesis
DeBrunner, Victor, committee member
Harvey, Bruce A., committee member
Department of Electrical and Computer Engineering, degree granting department
Florida State University, degree granting institution
Type of Resource: text
Genre: Text
Issuance: monographic
Date Issued: 2009
Publisher: Florida State University
Place of Publication: Tallahassee, Florida
Physical Form: computer
online resource
Extent: 1 online resource
Language(s): English
Abstract/Description: Multiple constant multiplications (MCM) is an optimization technique that is well-suited to DSP implementations. Using MCM, all coefficient multiplications are grouped into one efficient block of wired shifts and adds. A disadvantage of using MCM is the requirement of knowing the filter coefficients {it a priori}. Due to this limitation, MCM optimizations cannot be used in many applications. We propose a programmable adder graph (PAG) circuit that can implement multiplication using shift and add techniques without prior knowledge of the multiplier value. The PAG circuit allows any programmable device to be optimized using MCM for a wide range of DSP applications, including adaptive filters.
Identifier: FSU_migr_etd-3725 (IID)
Submitted Note: A Thesis submitted to the Department of Electrical & Computer Engineering in partial fulfillment of the requirements for the degree of Master of Science.
Degree Awarded: Spring Semester, 2009.
Date of Defense: December 1, 2008.
Keywords: Adaptive Filters, Multiplier Block, Directed Graph, Multiplierless, Field Programmable Gate Arrays
Bibliography Note: Includes bibliographical references.
Advisory Committee: Linda S. DeBrunner, Professor Directing Thesis; Victor DeBrunner, Committee Member; Bruce A. Harvey, Committee Member.
Subject(s): Electrical engineering
Computer engineering
Engineering
Persistent Link to This Record: http://purl.flvc.org/fsu/fd/FSU_migr_etd-3725
Owner Institution: FSU

Choose the citation style.
Howard, C. D. (2009). Minimizing FIR Filter Designs Implemented in FPGAs Utilizing Minimized Adder Graph Techniques. Retrieved from http://purl.flvc.org/fsu/fd/FSU_migr_etd-3725