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Design of Custom Instruction Set for FFT Using FPGA-Based Nios Processors

Title: Design of Custom Instruction Set for FFT Using FPGA-Based Nios Processors.
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Name(s): Sunkara, Divya Lakshmi, author
Meyer-Baese, Uwe, professor directing thesis
Meyer-Baese, Anke, committee member
Walker, Shonda, committee member
Department of Electrical and Computer Engineering, degree granting department
Florida State University, degree granting institution
Type of Resource: text
Genre: Text
Issuance: monographic
Date Issued: 2004
Publisher: Florida State University
Florida State University
Place of Publication: Tallahassee, Florida
Physical Form: computer
online resource
Extent: 1 online resource
Language(s): English
Abstract/Description: Nios Embedded processors provide a powerful, robust platform for developing and implementing complex algorithms. The unique custom instruction feature of Nios processors could be used to enhance the performance of these algorithms dramatically, while reducing the size and complexity of software. This feature involves implementing a part or entire algorithm in hardware and making it accessible to software through specially generated software macros known as custom instructions. Currently, fast Fourier transform (FFT) algorithms play an important role in many of the digital signal processing applications that are highly time critical. Hence there is a need to increase the performance of these algorithms. In the thesis, the decimation-in-frequency radix-2 FFT is implemented using custom instruction for the butterfly processor present in the algorithm. The performance enhancement of the custom implementation of this algorithm is then measured against software-only implementation.
Identifier: FSU_migr_etd-1499 (IID)
Submitted Note: A Thesis Submitted to the Department of Electrical and Computer Engineering in Partial Fulfillment of the Requirements for the Degree of Master of Science.
Degree Awarded: Summer Semester, 2004.
Date of Defense: June 17, 2004.
Keywords: CPLD, FPGA, Embedded processor, Soft-core microprocessor, Radix-2 FFT, RISC Architecture
Bibliography Note: Includes bibliographical references.
Advisory committee: Uwe Meyer-Baese, Professor Directing Thesis; Anke Meyer-Baese, Committee Member; Shonda Walker, Committee Member.
Subject(s): Electrical engineering
Computer engineering
Persistent Link to This Record: http://purl.flvc.org/fsu/fd/FSU_migr_etd-1499
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Host Institution: FSU

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Sunkara, D. L. (2004). Design of Custom Instruction Set for FFT Using FPGA-Based Nios Processors. Retrieved from http://purl.flvc.org/fsu/fd/FSU_migr_etd-1499