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Core Monitors

Title: Core Monitors: Monitoring Performance in Multicore Processors.
Name(s): West, Paul E., author
Department of Computer Science, degree granting department
Florida State University, degree granting institution
Type of Resource: text
Genre: Text
Issuance: monographic
Date Issued: 2008
Publisher: Florida State University
Place of Publication: Tallahassee, Florida
Physical Form: computer
online resource
Extent: 1 online resource
Language(s): English
Abstract/Description: Performance counters are becoming more complex as multi-core systems are becoming more wide spread. Consequently, evaluating these counters has become more complex as well. We propose providing hardware that monitors performance counters, namely in multi-core systems, in order to make decisions for improving performance. For instance, a piece of hardware watching snoop packets may be able to determine when a write-update cache coherence protocol would be helpful or detrimental to the current running program. Furthermore, watching memory traffic through a shared cache can determine if a program on a certain CPU is memory-bound. Once a program on a CPU is determined memory bound, the kernel can be informed to schedule accordingly. Finally, these new counters may be used to facilitate obtaining profile data for the compiler. We have implemented monitors in a full system simulator and found performance improvement.
Identifier: FSU_migr_etd-1156 (IID)
Submitted Note: A Thesis Submitted to the Department of Computer Science in Partial Fulfillment of the Requirements for the Degree of Master of Science.
Degree Awarded: Spring Semester, 2008.
Date of Defense: April 25, 2008.
Keywords: Multicore Architecture
Bibliography Note: Includes bibliographical references.
Subject(s): Computer science
Persistent Link to This Record:
Owner Institution: FSU

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West, P. E. (2008). Core Monitors: Monitoring Performance in Multicore Processors. Retrieved from